Developers of new systems should make decisions regarding clocking requirements early in the design process.Although clocking rates are critical parameters that should be known in advance, determining these rates sometimes requires experimentation and re-evaluation. The ability to quickly change clock frequencies during the prototyping and validation stages of a design can accelerate time to market.
The use of frequency-flexible, programmable crystal oscillators (XOs) as prototyping tools can facilitate the process of validating system performance and help streamline the overall product development cycle.
Evaluating Multiple Frequencies
When conducting any system design effort, frequency changes often become necessary late in the design cycle. In other cases, a bug or miscalculation in the design may require a change in frequency. In any of these situations, it helps to use XOs that are adaptable to last-minute changes without having to change the bill of materials or PCB layout, especially since lead time for fixed-frequency XOs may extend the development by weeks or even months.
Last-minute changes are very common, especially in FPGA-based applications. The extreme flexibility of FPGAs means that logic path widths and data rates can be quickly adapted to improve power, throughput or gate utilization.
Systems that use standard frequencies can also benefit from frequency-flexible XOs for design validation and frequency margining during production test. Although an Ethernet MAC or PHY may specify a 156.25 MHz reference XO, a fixed-frequency reference cannot exercise rate tolerances.
The disadvantages of this scheme include the limited number of frequencies and the introduction of additional noise and phase discontinuities that occur when switching between frequencies.
Using external clock sources or multiple XOs to perform frequency margining often limits the designer's ability to make fine frequency adjustments or validate a continuum of frequencies to troubleshoot suspected problem areas.
Traditional Frequency Flexible XOs Do Not Meet the Challenge
A better approach to the problem of performing frequency margining is to use in-circuit programmable XOs that can generate a continuum of frequencies with very high incremental frequency resolution without introducing phase glitching or compromising phase jitter performance.
To address this need, traditional XO suppliers use analog circuit techniques such as phase locked loops (PLLs) to overcome the frequency rigidity of conventional crystal oscillators. However, analog PLLs are often limited to powers-of-two or integer frequency multiplication.
Power Supply Rejection Performance Also Affects System Prototyping and Debug Time
Analog PLLs are notoriously sensitive to noise, often coupling
and amplifying noise sources through the power supply and internal VCO to the output clock signal. This sensitivity prevents analog PLLs from driving ultra-low jitter clock signals in high-performance systems where clocking flexibility is important and the environment tends to be noisy and hostile.
The system noise is largely due to transient load switching currents and the widespread use of switch mode power supplies (SMPS) in most computer, communications and consumer systems.
Integrated filtering and regulation translates directly into a BOM cost and component count savings since designers can minimize or even eliminate external power supply filters and ferrite bead components needed to maintain adequate jitter performance.
This reduced jitter performance makes common analog PLL-based XOs unsuitable for high speed networking applications, such as Gigabit (GbE) and 10 Gigabit Ethernet (10 GbE).
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